TABLE OF CONTENTS Packaging for aerospace systems is a reflection of the packaging approaches used in general. It can be recognised for the most part as having a modular hierarchy, spanning the connections of primitive elements within an IC to the cabling harness and chassis structures of an aerospace platform. The platform itself can be viewed as a package, as it recursively contains and interconnects lower levels of the hierarchy associated with particular platform designs. This section details an empirical taxonomy for packaging. This taxonomy has evolved quite independently from the influence of MEMS devices. The impact of MEMS on packaging is later examined as a separate topic.
The hierarchy of packaging for aerospace systems is depicted in FIGURE 9.10. The increasingly elaborate interconnections between transistors within an IC comprise the most basic level (L0) of the packaging hierarchy. The interface between the IC and its package is defined as level one (L1). A great diversity of L1 approaches exist, ranging from direct wafer-level/ chip-scale packaging to elaborate 2D and 3D packaging approaches. These latter approaches might be regarded as a sub-hierarchy within L1. Level two (L2) is typically a form of printed wiring board (PWB), which is an electrical/ mechanical substrate for packaged components. In systems having an integration complexity that requires more components than can be physically arranged onto a single board, other hierarchical levels are necessary. Most aerospace platforms have five levels (L0 L4), the last being the final platform itself.
