6.1 Introduction

Before an integrated circuit can be fabricated, one must specify the geometric patterns associated with the devices in it. These patterns are "laid out" highly magnified on a computer terminal screen. The name layout refers both to the drawing process and to the resulting drawings.

A layout drawing is often presented as a single overlay of the various masks; basic masks for the CMOS process have been shown in Fig. 5.2 (top of each part). The result of overlaying all these masks can be confusing, so color coding is typically used to help differentiate between different masks (e.g., yellow for wells, green for active regions, red for poly, blue for metal, black for contact windows, etc.). In this book we will use a simpler style for layout, which will be illustrated shortly. From this it will be easy to produce the layout of each mask for a given technology.

A number of layout rules must be followed during the layout process. These rules are devised for each fabrication process, from considerations such as reliability and immunity to undesirable effects (e.g., breakdown and latch-up). Examples of possible rules are "poly regions should be not narrower than 1 ?m," and "wells should be no closer to each other than 5 ?m." By the time all layers and their proximity or overlap in various combinations are considered, one ends up with several dozen such rules. The rules vary, depending on the fabrication facility and type of process...