5.3.1 Adding high-performance bipolar transistors to CMOS

In the CMOS process we discussed in the previous section, the bipolar transistors available were seen to be just by-products; such processes are optimized to provide good MOS transistors, and as a result the performance of the bipolar by-products is poor. However, with extra fabrication steps one can create processes that make possible both CMOS devices and optimized bipolar transistors. These are called BiCMOS (bipolar CMOS) processes. Such processes [ ^[30]] add flexibility to circuit design at an increased fabrication cost. As an example, consider the n-well CMOS process of Fig. 5.1 as a starting point; in principle it can be converted to a BiCMOS process by adding fabrication steps to produce an npn bipolar transistor on the same chip, as shown in Fig. 5.14a and b. An extra p-type diffusion forms the transistor's base. An n ⁺ buried layer is used to make possible a low collector series resistance. To further lower this resistance, a deep n ⁺ diffusion can be used, as shown. In contrast to the vertical by-product bipolar transistor in standard CMOS processes (Sec. 5.2.5), here all terminals of the device are available to the circuit designer. This is indicated in Fig. 5.14c. The well-substrate junction accompanies the device as shown, since the p-type substrate is permanently connected to ? V _SS (see also Fig. 5.1). BiCMOS processes with cutoff frequencies in the 5- to...