Silicon RF Power MOSFETS
Providing general guidelines for understanding the design and operation of the transistors, this book describes the physics, design considerations and RF performance of silicon power MOSFETs.
TABLE OF CONTENTS Silicon RF Power MOSFETS
3.3: Power MOSFET On-Resistance
3.3 Power MOSFET On-Resistance
As discussed in Chapter 2, the RF output power that can be delivered using a power MOSFET can be reduced by its on-resistance because it limits the lowest excursion of the drain voltage. The on-resistance of a power MOSFET is dependent upon contributions from various portions of the device through which the drain current flows. In this section, a simple analytical analysis of the on-resistance is provided as a guideline. An accurate value for the on-resistance can be extracted using numerical simulations as discussed later for specific device structures.
Planar D-MOSFET Structure
In the planar vertical D-MOSFET structure, shown in Fig. 3.1, the drain current flows from the source region through the channel region, the accumulation region, the JFET region, and the drift region. In addition, resistance contributions from the N + substrate and the contacts must be included in the analysis. The resistances of these regions have been described in detail in [3].
The channel resistance per unit area (R CH,sp) is given by:
where L CH is the channel length, L G is the gate width, m is half the polysilicon window, ? inv is the channel inversion layer mobility, C ox is the specific oxide capacitance, V G is the gate bias and V T is the threshold voltage. A low channel resistance contribution can be achieved by reducing the channel length and gate oxide thickness. A smaller cell pitch (2m + 2L G
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