Designing Digital Computer Systems with Verilog
Using Verilog, a leading commercial hardware description language, this text describes how to specify, design, and test a complete digital system.
TABLE OF CONTENTS Designing Digital Computer Systems with Verilog
Chapter 1: Controlling Complexity
Technical skill is mastery of complexity while creativity is mastery of simplicity.
E. Christopher Zeeman, Catastrophe Theory, 1977
The goal of this text is to teach you how to design a processor from scratch. In a step-by-step process, we will teach you how to specify, design, and test a processor as an example of a complex digital system. We will use the commercially important Verilog hardware description language (HDL) as the basis for this design process.
In particular, we will develop the VeSPA ( Very Small Processor Architecture) processor as a vehicle for demonstrating the overall design process. We show how the instruction set for this processor is defined, how to build an assembler for the processor, how to develop a behavioral simulator in Verilog to test the instruction set and the assembler, and how to develop a complete Verilog structural model of a pipelined implementation of the processor. We also describe the synthesis process for automatically translating this structural model into a real piece of silicon hardware. We end by demonstrating several techniques that can be used to verify the correctness of the processor design.
1.1 Hierarchical Design Flow
The development of any type of digital computing system is fundamentally a problem of controlling complexity. The designer of a large-scale digital system, such as a processor, begins with a high-level idea of what tasks the system is to perform. To realize this system in some physical technology, such as a collection of VLSI (Very Large-Scale Integrated circuit) silicon...
Copyright D. Lilja and S. Sapatnekar 2005 under license agreement with Books24x7
