Designing Digital Computer Systems with Verilog
Using Verilog, a leading commercial hardware description language, this text describes how to specify, design, and test a complete digital system.
TABLE OF CONTENTS Designing Digital Computer Systems with Verilog
VeSPA Instruction Set
| Mnemonic | Opcode | Operation | |
|---|---|---|---|
| Decimal | Binary | ||
| NOP | 0 | 00000 | No operation |
| ADD | 1 | 00001 | Addition |
| SUB | 2 | 00010 | Subtraction |
| OR | 3 | 00011 | Bit-wise logical OR |
| AND | 4 | 00100 | Bit-wise logical AND |
| NOT | 5 | 00101 | Bit-wise logical complement |
| XOR | 6 | 00110 | Bit-wise exclusive-OR |
| CMP | 7 | 00111 | Arithmetic comparison |
| Bxx | 8 | 01000 | Conditional branch (xx = condition) |
| JMP | 9 | 01001 | Jump indirectly through a register + offset |
| JMPL | 9 | 01001 | Jump and link indirectly through a register + offset |
| LD | 10 | 01010 | Load direct from memory |
| LDI | 11 | 01011 | Load an immediate value |
| LDX | 12 | 01100 | Load indirect through index register + offset |
| ST | 13 | 01101 | Store direct to memory |
| STX | 14 | 01110 | Store indirect through index register + offset |
| HLT | 31 | 11111 | Halt execution |
| Assembler pseudo-operations | |||
| MOV | 1 | 00001 | Move (copy) one register to another. This instruction actually is a pseudo-op that is converted to an ADD by the assembler. |
VeSPA Instruction Format
| Bit position | 31 27 | 26 23 | 22 | 21 17 | 16 | 15 11 | 10 0 |
|---|---|---|---|---|---|---|---|
| Instruction | |||||||
| ADD, AND,... |
Copyright D. Lilja and S. Sapatnekar 2005 under license agreement with Books24x7
