High Performance ASIC Design: Using Synthesizable Domino Logic in an ASIC Flow

| ASIC | application-specific integrated circuit |
| CMOS | complementary metal oxide semiconductor |
| CSA | carry save adder |
| CTO | clock tree optimization |
| DRC | design rule check |
| DSPF | detailed standard parasitic format |
| DVD | digital video disc |
| ECO | engineering change order |
| EDA | electronic design automation |
| FET | field effect transistor |
| fF | femtofarad |
| FO4 | fan-out of four |
| GHz | gigahertz |
| HDL | hardware description language |
| LFSR | linear feedback shift register |
| LSB | least significant bit |
| LVS | layout versus schematic |
| MHz | megahertz |
| MIPS | million instructions per second |
| MPC | minimum physical constraints |
| MPWH | minimum pulse width high |
| MPWHO | minimum pulse width high overlap |
| MPWL | minimum pulse width low |
| MSB | most significant bit |
| MUX | multiplexer |
| NMOS | n-channel metal oxide semiconductor |
| PLL | phase locked loop |
| PMOS | p-channel metal oxide semiconductor |
| PUT | pin under test |
| PVT | process, voltage, and temperature |
| QoR | quality of results |
| RC | resistor capacitor circuit |
| RF | radio frequency |
| RISC | reduced instruction set computer |
| RTL | register transfer level |
| SDC | Synopsys design constraints |
| SOC | system-on-chip |
| SRAM | static random access memory |
| TAT | turnaround time |
| VCO | voltage-controlled oscillator |
| VLSI | very large scale integration |
| XNOR | exclusive NOR |
| XOR | exclusive OR |
| m | micrometer |