TABLE OF CONTENTS We have described the unate and phase-assignment processes needed in domino synthesis. In this section we describe a synthesizable domino logic RTL to GDS flow designed for a 130 nm CMOS process that was subsequently refined for a 90 nm process. The flow is based on an existing static flow, with modifications being made, where needed, to support domino logic synthesis. While this flow description is specific to a set of tools, depending on the availability of EDA tools the domino synthesis flow can be modified. This is a similar situation to static logic, where flows are modified as tools and features improve.
Figure 4.2 shows the steps in the domino logic flow. The flow starts with a standard static RTL synthesis. This step uses Synopsys s Design Compiler?. The design is subsequently unated by applying bubble pushing. This is also done within Design Compiler?. Since logic is changed during the unate step, an incremental compile optimization is subsequently performed.
The domino logic block is then placed. This step is done with Synopsys s Physical Compiler?. Based on the actual arrival times on the input data pins, clock phases are next assigned to the domino cells. This analysis is done using PrimeTime?, with the required netlist modifications (cell replacement, buffer insertion) executed by means of an incremental optimization in Synopsys s Physical Compiler?. After placement, the clock tree synthesis and routing is performed. For this too a Synopsys tool is used:...
