TABLE OF CONTENTS The second domino-specific step needed in domino synthesis is phase assignment. During phase assignment the pseudo-static library is replaced by one having the full domino timing model. The clock pin is now visible in the domino cells and needs to be attached to the proper clock phase. Since timing data is very important in the phase assignment procedure, this task is done after placement so that actual wiring delays can be considered. Attaching clock phases to domino cells not only specifies the timing relationship of the final design, but also determines if the design is functional. It is possible to apply a number of different clocking schemes to domino designs. For our purposes a four-phase clocking scheme (with each clock having a 50% duty cycle) is the preferred domino clocking methodology as it reduces the skew requirements on the clock [1].
What makes the phase assignment process difficult is that the synthesis process is performed only under worst-case evaluate cycle conditions. This is necessary as no current, commercially available synthesis tool can understand the dual operating mode of domino logic. Using the evaluate cycle delays to perform synthesis is a reasonable assumption, since it is the critical condition for well-conditioned domino circuits. Nevertheless, the precharge cycle is also important, especially when we start including non-clocked cells in the design. Complicating the matter further is that precharge delays must be considered for both the fast and slow process and environmental corners, to test for...
