TABLE OF CONTENTS The phase-assignment process for domino cells assigns an initial preferred clock phase to each cell based on the arrival time of the last rising data input. Cells with inputs arriving in the first quarter of the clock period will be clocked by phase 
1, while if the inputs arrive in the second quarter of the clock period they will be clocked by phase 2, and so on. Such a straightforward scheme has some problems which need to be corrected. We describe these problems next, along with how they can be overcome.
Domino cells on a non-critical, weakly driven path may have a driver cell on phase 1 and the receiver cell two phases later. Phase skipping of two phases involves a potential race between the clock skew of the two cells versus the precharge delay of the driving cell. Figure 4.5 illustrates how skew can lead to a high value at s1 not being captured in cell B. This is a hold time failure.
Risk evaluation. Since all the initial synthesis is done to meet worst-case process and environmental conditions, a quick risk evaluation can be made by asking if the problem described is more serious for typical silicon. If so, it is a serious problem. A similar, but slightly different, formulation of risk evaluation can be made by asking if the problem is less likely to occur when the design is run...
