6.1 Introduction

VLSI interconnect modeling and optimization is an important step toward highspeed electronic system design. With rapid developments in VLSI technology, design, and CAD techniques at both chip and package levels the central processor cycle times are reaching the vicinity of 1 ns. The communication switches are now being designed to transmit data at bit rates faster than 1 Gbps. At such high signal speeds, previously negligible interconnect effects such as signal delay, crosstalk, ground noise, ringing, and distortion become significant [1 5]. These interconnect effects also known as signal integrity effects (described by analog analysis techniques) must be taken into account during digital circuit design. In addition, the drive within the VLSI industrytoward miniature designs, low power consumption, and increased integration of analog circuits with digital blocks, has further complicated the issue of signal integrity analysis. The scaling of chip dimensions to achieve miniaturization and high signal speed affects the global interconnect delay. As shown in Figure 6.1, the global interconnect delay grows as a cubic power of the scaling factor ( ? 1) [1, 6]. It is predicted that interconnects will be responsible for nearly...