Overview

The Peripheral Component Interconnect (PCI) architecture is well-established and widely implemented in the industry. Initially defined as a parallel 32-bit, 33-MHz interface, PCI as the specification extension PCI-X has developed to include a 64-bit wide parallel bus at transfer rates of 133 MHz, with specification extensions to allow for higher parallel data rates. While the specifications allow higher data rates, a single- ended, parallel bus has a limited technological capacity.

PCI Express , the high-speed signaling extension to the Conventional PCI and PCI-X architectures, provides a signaling architecture that supports the higher data rates. Initially defined at 2.5 billion transfers per second (2.5 GT/s), the PCI Express signaling architecture will be extended to sustain the higher data rates needed to satisfy future performance needs.

PCI Express preserves the Conventional PCI load/store programming model, but incorporates three significant changes:

• PCI Express has an embedded clock. Unlike Conventional PCI and PCI-X, PCI Express data signal timing doesn't utilize an external clock or strobe signal to qualify the data. The PCI Express clock is embedded in the data signal itself. This eliminates the data-to-clock setup and hold time constraints and the data path-to- clock path timing skew.

• PCI Express signaling is differential, not single-ended as are Conventional PCI and PCI-X. With differential signaling, the "difference" in the D+ and D- signals of each signal differential pair constitutes the signal amplitude, not the signal to...