TABLE OF CONTENTS This chapter describes a system-level time domain simulation, including a model of a PCI Express interconnect channel constructed using the signal integrity modeling method discussed in Chapter 2. Performing time domain simulation requires that you know the following parameters:
Driver model with corner cases
Receiver load model
Package model
Connector and via models
Printed circuit board (PCB) model with parametric variations
Minimum acceptable voltage and time levels at the receiver pins
Worst-case data pattern
Mode conversions
This chapter covers the following topics:
Excitation patterns of a PCI Express channel to measure the following terms: inter-symbol interference (ISI), crosstalk, and simultaneous switching outputs (SSO)
Design of Experiment (DOE) analyses, focusing on finding the solution space based on the sensitivity of the sweep parameters
Eye voltage margin and jitter modeling methods
For PCI Express differential busses, time domain data typically are measured in terms of three voltage modes:
Differential mode voltage, defined as (V D+ - V D-)
Common mode voltage, defined as (V D+ + V D ) / (2 - VCM_avg)
Single-ended mode voltage, defined as V D+ or V D
The most important of the three modes is differential mode voltage. However, both single-ended mode voltage and common mode voltage are also significant, so you should know how to measure all three voltages.
Another phenomenon plays a significant role in the PCI Express differential busses. Mode conversion is defined as a transformation of the differential mode voltage to...
