TABLE OF CONTENTS The PCI Express electrical interconnect channel is a point-to-point, low-voltage swing differential (LVSD) bus, operating at 2.5 GT/s per differential pairs. An advantage of LVSD signaling is providing a great flexibility for high-speed design, including a greater bandwidth per pin. The PCI Express electrical interconnect channel needs careful modeling and validation methods to support a robust and reliable operation. This chapter presents detailed simulation models for all elements of the PCI Express interconnect channel, and discusses design challenges and ways to achieve the best performance.
The PCI Express interconnect design must specify the loss on each interconnect element as well as the defined boundaries between segmented elements. From a platform viewpoint, the end-to-end loss must include and specify the package and interconnect characteristics. In the loss-based method, the package characteristics are defined at the package pins, including the driver and/or receiver on-die capacitance to include impact of the package on the interconnect loss budget.
In this method, you model the package and die as a single entity. For the package design, you can model the package by measuring the frequency domain data, S-parameters, and the time domain data that is, the voltage eye measured at the package pins, where the interconnect system is terminated into an ideal 100 ? differential test load. Most designers find it helpful to characterize the receiver in the same way when it is excited by a controllable differential source to obtain a minimum eye at the package pins.
In the...
