TABLE OF CONTENTS By understanding the topology-related aspects of the PCI Express specification, you can plan effectively and implement your design with greater confidence. As discussed in Chapter 1, certain connectivity rules and conventions apply to PCI Express signals just as with any other interface. However, some inherent features that are built into the specification make your life as the system designer somewhat easier.
As you learn to apply the PCI Express specification's connectivity rules to your designs, you can take full advantage of the allowances for PCI Express topologies and layouts. The following requirements and guidelines apply specifically to connectivity:
Each connection between PCI Express devices must be point-to-point. In other words, a connection can only exist between one driver and one receiver. Daisy-chaining, or connections of multiple transmitters and receivers on one wire or interconnect, is not allowed. You should make sure that all components in your designs are routed such that they directly connect with just one other PCI Express component.
Do not confuse this rule with link bifurcation and link width negotiation, in which point-to-point lanes are grouped together to form up to x32 links between two separate devices. For more on link width negotiation and bifurcation, see Chapter 1.
The PCI Express specification dictates that each lane of a link be AC-coupled between its corresponding transmitter and receiver. The AC coupling capacitance is required either within the transmitter component/package or along the interconnect link on the Printed...
