The clocking requirements for PCI Express topologies differ from those of most other interconnects. As explained in Chapter 1, unlike most common clock designs, PCI Express interconnects no longer require a clock-to-data timing relationship to be enforced. As the system designer, having no clock-to-data timing relationship to worry about means your life just got a whole lot easier! By understanding the implications of the embedded clocking nature of PCI Express components, you can improve the performance and simplify the layout of your PCI Express interconnects.

The "embedded clock" feature of the specification essentially means that components in a PCI Express link can extract the data timing and phase information directly from the data stream, rather than having to rely on strict setup and hold times between the data bits and a clock provided by the system. Most of your PCI Express components only require that you provide them with a differential seed or reference clock of the same frequency supplied to other PCI Express components on the same link. The components can use this frequency reference, along with the phase information they extract from the data stream, to adequately sample the data bits they receive.

As mentioned previously, you no longer need to worry about clockto-data signal phase and skew relationships; the only thing that matters is the relative frequency of the clocks themselves. On the system board, this narrowed focus translates into the removal of any cumbersome serpentine trace routes that you might be accustomed...