TABLE OF CONTENTS A recent arrival for flip-chip RF modules is a copper pillar bump (see Figures 4.18 and 4.19). The main benefit is its improved thermal dissipation [30], as demonstrated in Chapter 3. However, the advantages of copper pillar bumping include fine-pitch, repeatable height, better thermal performance, and better electrical performance [31]. Better thermal and electrical performance are obviously an advantage, but so is uniform height, since it is required for mating to the module substrate. However, the pillars are constructed through a plating process that is slower throughput than a solder bumping process and hence more costly. The cost of this process is offset by a number of cost savings factors for the die that utilizes this approach. Three main factors allow for a reduction in die cost. The first is the elimination of the backside via process, an expensive, slow process that can result in die yield issues. A completely metal-filled via will cause die cracking over thermal cycling from power dissipation under normal operation. The filling of the via must be tightly controlled to avoid these thermal reliability issues. The second factor is the reduction in die size for the copper pillar approach, which arises from the removal of the large vias as well as the removal of the large wire bond pads on the outer edge of the die. The last factor is the removal of the wafer backgrind or thinning process. GaAs die have been thinned to 50 m in extreme cases for...
