TABLE OF CONTENTS Most of the techniques described in this chapter increase cost over the other available processes, but they provide smaller solutions or better performance. A detailed analysis is required to determine the overall module cost with these techniques versus other solutions. In many but not all cases, these techniques can reduce the overall module cost through smaller modules and less passive components [48]. They also allow for incorporation into one of the lowest-cost package options available, MLF/QFN. Using a silicon IPN within a MLF/QFN package can eliminate a more expensive multilayer laminate or LTCC substrate. The package may consist of only two die. A passive silicon IPN was stacked on top of an active BiCMOS die within an MLF/QFN package for a low-cost solution [49]. However, die alone is not the only option for the new vintage MLF/QFN packages. In addition to die, discrete passive components can also be added to the MLF/QFN package.
The leadframe MFL/QFN package limits the main option for die to package interconnect as wire bond. One of the main objectives of flip chip is to shrink the die by making the I/O in an array with fine pitch. The 6-mil line and spacing design rules for leadframe MLF/QFN dictates a wide pitch of 12 mils. This is contrary to the flip-chip approach; however, flip chip can be incorporated into an MLF/QFN package [50]. Except for a few designs where the flip chip utilizes wide I/O pitch, the majority of...
