The CMOS SAR ADC is a sampling system that takes one sample for every conversion. The analog input signal to a SAR converter first sees a switch and a capacitive array, as shown in Figure 13-6. The input node connects a capacitive array on one side and the noninverting input to a comparator on the other.

Figure 13-6: The modern SAR converter uses a capacitive array at the analog input. This capacitive array and the remainder of the device are easily manufactured in CMOS, making it easy to integrate with microcontrollers or microprocessors

When the switch ( S ₁) is closed, the voltage input signal is sampled onto the internal capacitive array of the converter. After the sampling time is completed, S ₁ is opened and the bottom side of the most significant bit (MSB) capacitor is connected to V _REF while the other capacitors are tied to V _SS (or the system ground). The charge from the MSB capacitor is redistributed among the other capacitors. The charge is distributed across the capacitor array, and the noninverting input of the comparator moves up or down according to the voltage presented at its input. The voltage at the noninverting input of the comparator, with respect to V _SS, is equal to (1/2 V _DD ? V _IN) +1/2 V _REF. If this voltage is greater than 1/2 V _DD, the MSB is equal to zero, which is transmitted...