1.0 INTRODUCTION

Polishing of materials has been known to many disciplines for many decades. For example, in astronomy, glass mirrors and lenses have been polished since at least the seventeenth century. In metallurgy, metal samples are routinely polished prior to metallographic examination. In the semiconductor field, lapping and polishing have been used for the preparation of single crystal substrates (wafers) during the last 40 years. The lapping process is used after sawing and prior to polishing. Lapping is performed on both sides of the wafer to insure flatness and parallelism. Polishing is used to remove surface damage and haze. All polishing processes described above refer to the surface finishing of bulk materials. During the past decade, a new application of polishing has occurred in integrated circuit manufacturing. This application involves the removal of thin metal, insulator, and semiconductor films. This new field is referred to as chemical mechanical polishing (CMP).

The primary driving force for CMP was the realization during the 1980s that shrinking feature size and the increased number of devices on a chip required additional layers of metallization (separated by interlayer dielectrics, ILD). Since the metal layers were etched into metal lines, and the ILD layers were deposited by conformal CVD processes, additional metal layers meant that there would be a dramatic increase in topography within the die. This effect is illustrated in Fig. 1. This increase in topography was in direct opposition to trends in lithography where the printing of ever-smaller feature sizes...