1.0 INTRODUCTION

The fabrication of submicron microelectronic devices in semiconducting crystals requires inducing a wide variety of physical and chemical processes. Epitaxy, oxidation, lithography, etching, ion implantation, and deposition all must be carried out with a high degree of process control and spatial uniformity. As device and feature sizes shrink below one micron, the inherent limitations of traditional furnace-based thermal processing methods become manifest. Foremost, we must reduce the total time-temperature cycling required to complete fabrication steps.[1] This reduction is motivated by the need to minimize thermal diffusion and its associated redistribution of as-implanted doping profiles, to reduce thermal defect creation and migration in the crystalline substrate, and to minimize thermally-induced substrate warpage as required by submicron lithography. When fabricating submicron feature sizes, there is also a need to process materials with a minimum amount of process-induced radiation damage,[2] such as that found in plasma etching or deposition, electron or ion beam lithography, and ion implantation.

One way to exert a high degree of spatial and temporal control over the energy input to any processing step is through the use of directed energy beams which are created with both high energy selectivity and spatial directionality. Ion beams, for example, have long been used to implant dopant species with repeatable doses and specific depth profiles. The recent use of ion beam lithography and direct write pattern transfer has also shown promise.[3][4] Photon and electron beams have also long been...