Phase-Locked Loop Engineering Handbook for Integrated Circuits

This chapter covers simulation techniques for PLLs. The types of PLL simulators vary from SPICE transistor-level solutions, to behavioral-model solutions, to equation-based solutions. Transistor-level simulations are presented to show the many conditions that can be tested using this method. The characteristics of supply-voltage sensitivity responses, pulse feed-through levels, slew rate, powering up, powering down, and loop recovery from supply-rail conditions are unique conditions that are shown.
Behavioral-model simulations are presented to show that significant improvement in computing time with a minimum loss of accuracy can be achieved. The advantages and disadvantages of the model are discussed, and an example simulation is done to show its performance. Finally, an example of numerical errors is shown to give some insight into the types of errors that can occur with a behavioral model. Difference-equation-based simulations are presented not only to show increased computing speed but to show unique characteristics of digital PLL simulations. The speed of the behavioral and difference-equation models allow many iterations of what-if questions to be studied. The choice of simulation depends on the speed and accuracy of the results. For instance, accurate SPICE simulations can take several weeks to run when looking at acquisition times. This chapter will help the reader make an informed choice between methods.
In this section, we will study transistor-level simulations. An example PLL will be used to show transistor-level simulation characteristics that could not be studied using behavioral models or equation-based simulators. Power-on from both supply rails, small frequency step response,...