TABLE OF CONTENTS The main concern for jitter in digital systems is the decrease in timing margin that it causes. Controlling jitter allows more flexibility in the timing budget.
For example, Figure 3.31 shows the effect of jitter on the edge-to-edge timing margin. A positive skew results in the final register ( U 2) of the data path that leads the time of arrival of the clock signal at the initial register ( U 1). Under these conditions, the maximum attainable operating frequency is decreased (worst case). Equations (3.85) through (3.87) calculate the effects of jitter on the timing margin [23]:
The effects of jitter have three main components in the frequency domain. These components are close-to-the-carrier phase noise, far-from-the-carrier phase noise, and spurious signals. The highest levels in silicon are spurious signals. The following are causes of jitter from spurious signals [24]:
Data/clock dependency;
Conducted (e.g., switching power supply, motors, relays);
Simultaneous switching outputs (SSOs) or ground bounce;
Crosstalk;
Reflections;
EMI;
Low loop stability of <10 phase margin in a control loop.
Figure 3.32 shows possible injection paths into a PLL that can cause jitter. The most sensitive spot in any PLL is the voltage-controlled oscillator's tune line because it usually has high-gain and high-impedance characteristics. Next, the power-supply lines to the VCO are usually sensitive. Recent measurements have shown that output buffer switching...
