Overview

This chapter presents loop-compensation synthesis. The synthesis of loop-compensation components in the loop is application dependent. Consequently, several examples of the most popular compensation schemes are presented. This gives us an intuitive feel to extend these methods to designs that are not presented. These examples include the following design types:

• Passive;

• Active with maximum capacitor value;

• Sampling delay;

• Fast switching time;

• Minimum bandwidth;

• Maximum divide ratio;

• Optimum low phase-noise.

This chapter begins by ranking PLL requirements to help make the design trade-offs that optimize a PLL loop compensation for an application. Ideal design requirements for a synthesizer and a clock-recovery circuit are presented. Next, a nine-step cookbook method for doing compensation is presented to ease making decisions about the trade-offs in PLLs. For beginning- and intermediate-level PLL designers, it is best to start with the cookbook method. An example shows how to apply the cookbook method. Next, a simple example to illustrate the technique for active compensation and maximum capacitor value is presented. The biggest impact on IC design is the area of the capacitor in silicon. The limitations of the components in this low area PLL architecture are explored. The next example illustrates the technique for active compensation and compensating the design for sampling delay. Sampling delay is a major limitation to widening the loop bandwidth. At the limit of the sampling delay, the loop loses stability. A derivation of the new design equations that accounts for sampling delay is presented. Another example illustrates the technique for obtaining...