H 264 Decoder Chips

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  • Image progressive acquisition for hardware systems
    He, J. Zhu, J. Kong, P. Liu, and S. Goto, “A 530 mpixels/s 4096x2160@ 60fps h . 264 /avc high profile video decoder chip ,” Solid-State Circuits, IEEE Journal of, vol.
  • Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications
    H . 264 HDTV decoder using application-specific networks-on- chip .
  • 2006 Index
    … at 80 gbit/s; J-SC Oct 06 2215- 2223 Makris, Y., see Stratigopoulos, H .-G.D., J … A 640-Mb/s 2048-bit programmable LDPC decoder chip ; J-SC Mar 06 684-698 Mantyniemi, A., see Jansson, J.-P., J-SC Jun 06 … … Jan 06 179-196 Mathew, S.K., see Hsu, S.K., J-SC Jan 06 256- 264 .
  • Design of on-chip error correction systems for multilevel NOR and NAND flash memories
    Electron Devices, 2002, 23, pp. 264 –266 23 Takeuchi, K., Tanaka, T., and Nakamura, H .: ‘A double-level-Vth select gate array architecture for multilevel NAND … … et al.: ‘A 0.13-mm CMOS NOR flash memory experimental chip for 4-b/cell digital … … 2002, pp. 131–134 25 Chen, Y., and Parhi, K.K.: ‘Area efficient parallel decoder architecture for long …
  • Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
    … Nano-Net’06), September 2006, pp. 1–5 10 Jiang, X., Wolf, W., Henkel, J., Chakradhar, S.: ‘ H . 264 HDTV decoder using application-specific networks-on- chip ’.
  • 2013 Index IEEE Transactions on Signal Processing Vol. 61
    Particle Based Smoothed Marginal MAP Estimation for General State Space Models; TSP Jan. 15, 2013 264 -273 Sahin, O., see Park, S. - H ., TSP Nov. 15, 2013 5646-5658 Salapaka, M. V., see Kumar, N., TSP July 15, 2013 3647-3652 Salvo … A First Step Toward On- Chip Memory Mapping for Parallel Turbo and LDPC Decoders : A Polynomial Time Map- ping Algorithm; TSP Aug. 15, 2013 4127-4140 Sanquer, M., Chatelain, F., El-Guedri, M., and Martin, N., .
  • A 110-K transistor 25-MPixels/s configurable image transform processor unit
    [7] S. Rao et al., “A real-time P 264 /MPEG video encoder chip ,” in IEEE Int. [8] D. Brinthaupt et al., “A video decoder for H .261 video teleconferencing and MPEG stored interactive video applications,” in IEEE Int.
  • A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices
    … Dec. 2005 [2] T.M. Liu, et al., “A 125 W, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications”, ISSCC … … Full 3D Pipeline with 264 Mtexels/s Texturing for Mobile … … 45, 2003 [4] J. H Sohn, et al., “A … Chip Feature Summary .
  • Digital Video
    Macroblock (MB), 147, 165, 246 header, 165 layer in H .263, 374 macroblock_address-increment, 165, 246 macroblock_intra, 254 macroblock_motion_backward, 247 macroblock_pattern, 247 macroblock_quant, 247 macroblock_type, 165, 247 macroblock_type VLCs, 251 Main Level, 263 Main Profile, 263, 264 Main profile at Main level … … vectors for chrominance pels, 154 motion_code, 155, 256 motion_residual, 154, 256 motion_vector_count, 254, 256 Movie Film, 3 Moving picture experts group (MPEG), xi, 9, 25 audio software, 418 chip development, 367 committee, 422 … … 22 audio encoder and decoder for Layer III, 67 …
  • Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory
    [32] J.-D. Lee, S.- H . Hur, and J.-D. Choi, “Effects of floating-gate interfer- ence … 23, no. 5, pp. 264 –266, May 2002. [34] M. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-bit program- mable LDPC decoder chip ,” IEEE J. Solid-State Circuits, vol.