JTAG Interface Software

Description: verifications include: • structural tests (structural validation of the hardware) • functional tests (functional validation of the modules) • integration tests (interface validation of the modules) • system tests (functional validation of the prototype) In addition, parametric tests with

• Applications: JTAG / Boundary Scan

Description: programs and sequences created in ProVision are backwards compatible with Classic tools and production software options. To support the ProVision and 'Classic' developer tools in production JTAG Technologies offers a complete range of integregation packages (PIPs) typically used for

• Applications: JTAG / Boundary Scan

Description: developed with MathWorks’s MatLab® software. The FPGA on Acromag’s IP-EP200 modules can control up to 48 TTL or 24 RS485 I/O signals or a mix of both types. Another model interfaces 24 LVDS I/O channels. User application programs are downloaded through the JTAG port or via the

• Number of Channels: 24
• Bus Width: 16-bit, 8-bit
• Clock Rate: 32 MHz, 8 MHz
• Features: Integrated Counter / Timers, Other, Programmable Channels

Description: is an essential tool for the resolution of complex software/hardware and timing-related issues, as it enables post-analysis of a software execution without the need for any software or hardware instrumentation. The 4 GB trace buffer on DSTREAM enables high-bandwidth trace for

• Bus Width: 16-Bit
• Manufacturer: ARM
• Development Tool: Debugger / Debug Probe
• Category: Development Suite / Kit

Description: it enables post-analysis of a software execution without the need for any software or hardware instrumentation. In addition, the innovative data streaming capability in RVT2, together with the ARM Profiler also enables non-intrusive, long term software profiling. RVI and RVT2

• Bus Width: 32-Bit, 64-Bit
• Manufacturer: ARM
• Development Tool: Debugger / Debug Probe
• Signal Type: Digital

Description: it enables post-analysis of a software execution without the need for any software or hardware instrumentation. In addition, the innovative data streaming capability in RVT2, together with the ARM Profiler also enables non-intrusive, long term software profiling. RVI and RVT2

• Bus Width: 32-Bit, 64-Bit
• Manufacturer: ARM
• Development Tool: Debugger / Debug Probe
• Signal Type: Digital

Description: a GNU-based complier and debugger, with optional JTAG support, all within an Eclipse based IDE. UI integration Create compelling user interfaces, without modifying source code, using Nucleus ReadyStart's built-in Inflexion UI tool: Inflexion UI Express helps developers implement a UI

Description: In-System Programming by On-chip Boot Program True Read-While-Write Operation Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug SupportProgramming of Flash,

• Operating Temperature: -40 to 85 C
• Device Type: Clock Generator
• Package Type: DIP
• Features: Other

Description: Microchip's LAN7431 is a PCIe 3.1 (at 2.5GT/s) to Reduced Gigabit Media Independent Interface (RGMII) Gigabit Networking bridge providing an ultra-high-performance and cost-effective PCIe to Ethernet connectivity solution. LAN7431 contains an integrated RGMII interface, PCIe PHY, PCIe

• Features: Bus Interface / Adapter

Description: The miniWiggler is Infineon’s high performance and cost-efficient debugging tool for the future. On the host side, it has an USB interface, which is available on every computer. On the device side, the communication goes over Infineon 10-pin DAP or 16-pin OCDSL1 interfaces. The

• Category: Development Board
• Features: Other

Description: The high-performance Microchip picoPower® 8-bit AVR® RISC-based microcontroller combines 32 KB Flash memory with read-while-write capabilities, 1 KB EEPROM, 2 KB SRAM, 69 general purpose I/O lines, 32 general purpose working registers, JTAG interface for boundary-scan, on-chip

• Internal RAM Size: 2.048 KB
• Internal ROM Size: 32 KB
• Number of Timers: 2
• Pin Count: 100

Description: +85 °C 12V DC Supply Platform for rapid product development Reference design for handheld data logging terminals Kit Contents: Hardware: eSOM270 Module Carrier board (Regulus) JTAG USB ActiveSync Cable LCD Daughter card with 4.3" / 7" TFT Touch Screen Stylus Power Supply Software:

• RAM: 128 MB
• Flash Memory (RAM): 32,000 to 512,000 KB
• Operating Temperature: -13 to 185 F
• Communication Networks: Ethernet

Description: ERF1000 eval kit - Evaluation kit for ERF1000 module Including: Three boards, battery holders, USB adapters, JTAG programmer and 2.4GHz antenna. Peripherals - With ethernet, 1 board (gateway) - Without ethernet, 2 boards (nodes) - 2.4GHz module (ERF1000) - USB port - RS232 - RS485 - IrDa

• Category: Development Board
• Supported System: Wireless Systems

Description: The high-performance, low-power Microchip 8-bit AVR RISC-based microcontroller combines 32KB ISP flash memory with read-while-write capabilities, 1KB EEPROM, 2KB SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for boundary-scan and on-chip

• Internal RAM Size: 2.048 KB
• Internal ROM Size: 32 KB
• Number of Timers: 2
• Pin Count: 64

Description: open chassis test environment. I2C and JTAG interfaces are provided for access to all receiver, transmitter, and other device configuration and status registers via IDT ’s Configuration Utility GUI for Windows. Software tools for signal eye capture are available.

• Category: Development Board
• Features: Other

Description: The AcroPack® product line updates our popular Industry Pack I/O modules with a PCIe interface format. This tech-refresh design offers a compact size, low-cost I/O, the same functionality and memory map of the existing Industry Pack modules. This board interfaces four AcroPack

• Operating Temperature: -40 to 185 F
• User Interface: Computer Programmable
• Host Connection: Direct Backplane Interface
• Application: General Lab and Industrial

Description: Authentication Random Number Generator (RNG) to assist security algorithms Peripherals SPI Master / Slave interface 3 x multi-channel serial digital interface (I²S, TDM) UART I²C Master I²C Slave 3 x 32-bit general-purpose timer modules Watchdog timer On-chip JTAG debug unit and

• Clock Speed: 260 MHz
• Operating Temperature: -40 to 85 C
• DMA Channels: 32
• Data Bus: 24-Bit

Description: Connectivity USB USB Version USB 2.0 CPU CPU Clock Speed Up to 650 MHz Software Options Operating System Linux Memory Memory Type DDR1 DDR2 Flash NAND NOR Interface Layers MAC PHY Supported Interfaces UART USB 2.0 I²C JTAG PCIe 1.1 Voltage Support 3.3V Input/Output

• Operating Frequency: 650 MHz
• Data Rate: 190,000 kbps
• Interface: I²C, PCI Express, USB
• Package Type: QFN

Description: JTAG interfaces are also provided to access all receiver, transmitter, and other device registers.

• Category: Development Board
• Features: Other

Description: I/O Interface Connector P1 (PCIe Bus): PCIe V2.1 x4 lane (PCIe Gen 2 Switch). J3 (Carrier Field I/O): 68-pin, stacked, CHAMP (TE Connectivity 5787962). P2, 3 (AcroPack Field I/O): 100-pin socket (Samtec SS5-50-3.00-L-D-K-RT). J1, 2 (Mini-PCIe): 52-pin socket (TE Connectivity 1759547-1). P6

• Module Voltage: -12 V, 12 V, 3.3 V, 5 V
• Carrier Class: Non-intelligent Carrier
• Features: Other

Description: JTAG interfaces are also provided to access all receiver, transmitter, and other device registers

• Category: Development Board
• Features: Other

Description: the programmable hardware side on-board (FPGA), reducing the data transfer over the slow JTAG interface. The resources of the FPGA are used to implement a complete FPGA based test system capable of generating, applying, and analyzing test patterns at high speeds. In this way, we reduce

Description: multi-purpose 12 bit ADC， AUDIO ADC, PPG Heart rate detection, Touch sensor controller. The HS6621 integrates on chip 256KB ROM, 256K SRAM and supports user defined IDE system, on chip SFLASH MCU development and JTAG software upgrade.

Description: I/O signals or a mix of both types. Another model interfaces 24 LVDS I/O channels. User application programs are downloaded through the JTAG port or via the IP bus directly into the FPGA. A pre-programmed internal CPLD facilitates initialization by acting as the bus controller during

• Operating Temperature: 0 to 70 C
• Features: FPGA
• I/O Interface: LVDS, TTL

Description: software, peripherals and development tools. Whether your design requires the lowest-priced 16-bit solution, the most powerful 16-bit MCU in the industry, or DSP capability, Microchip offers a broad range of products while preserving the compatibility that help save you time and money on

Description: software, peripherals and development tools. Whether your design requires the lowest-priced 16-bit solution, the most powerful 16-bit MCU in the industry, or DSP capability, Microchip offers a broad range of products while preserving the compatibility that help save you time and money on

Description: selectable on a per channel basis. The chip also provides driver shortcircuit protection and internal protection diode and supports JTAG boundary scanning. The chip can be controlled by either software or hardware. The IDT82V2042E can be used in LAN , WAN , Routers, Wireless Base

• T_J: -40 to 85 C
• Pin Count: 80 #
• Supply Voltage: 3.3 V
• Features: Other

Description: The EtherCAT SubDevice Controller ASIC ET1150 offers additional functions to those already included in the ET1100. drop-in compatible with ET1100 (3.3 V designs) single power supply option, integrated DC/DC increased DPRAM: 15 kB 16 FMMUs & 16 SyncManager dual process data interface (PDI) 4 x

• Data Acquisition: I/O Module

Description: P2) Optional video interface (VGA frame buffer) 1 * XMC slot PCIe x8 -or 2 * x4 (Option, with restriction - consult us) Miscellaneous Status Leds PIC μ-controller for System Management (VITA 46.11) Accessories Engineering kit for debug : JTAG/COP, console,... 3U Rear Transition Module

• RAM: 8,000 MB
• Communication Networks: Ethernet
• Processor / CPU: Intel® Xeon®
• Ports: Serial Ports, USB

Description: Extensive on-board temperature, voltage and current monitoring and logging capabilities Board Management Control on IPMC bus (VITA 46.11) On-board Elapsed Time Indicator Debug facilities through AURORA and JTAG on-board connector Interfaces (available with use of RTM): IPMC bus

• CPU Speed: 1,800 MHz
• RAM: 12,000 MB
• Flash Memory (RAM): 256,000 KB
• Communication Networks: Ethernet

Description: The XCalibur5090 is a high-performance, reconfigurable, conduction-cooled 6U LRM module based on the AMD (formerly Xilinx) Virtex-7 family of FPGAs. With a pair of Virtex-7 FPGA, high-speed serial interfaces, DAC and ADC channels, external memory, and flexible, high-density I/O, the

Description: gating. The CPU sub-system also includes a 16-channel DMA/Datawire block and a serial wire debug (SWD) interface, which is a two-wire form of JTAG. The debug configuration used for PMG1-S3 has four break-point (address) comparators and two watchpoint (data) comparators. EZ-PD™ PMG1-S3

• Internal RAM Size: 32 KB
• Supply Voltage (V_cc): 2.7 to 24 volts
• Operating Temperature: -40 to 85 C
• ROM Type: Flash

Description: connector. Its Cortex®-M0+ is a 32-bit MCU that is optimized for low-power operation with extensive clock gating. The CPU sub-system also includes a 16-channel DMA/Datawire block and a serial wire debug (SWD) interface, which is a two-wire form of JTAG. The debug configuration used for

• Internal RAM Size: 32 KB
• Supply Voltage (V_cc): 4 to 24 volts
• Operating Temperature: -40 to 85 C
• ROM Type: Flash