Dominant-pole compensation is the simplest kind, though its action is subtle. Simply take the lowest pole to hand (P1), and make it dominant, i.e., so much lower in frequency than the next pole P2 that the total loop-gain (i.e., the open-loop gain as reduced by the attenuation in the feedback network) falls below unity before enough phase-shift accumulates to cause HF oscillation. With a single pole, the gain must fall at 6 dB/octave, corresponding to a constant 90 phase shift. Thus the phase margin will be 90 , giving good stability.

Figure 7.1 a shows the traditional Miller method of creating a dominant pole. The collector pole of TR4 is lowered by adding the external Miller-capacitance Cdom to that which unavoidably exists as the internal Cbc of the VAS transistor. However, there are some other beneficial effects; Cdom causes pole-splitting, in which the pole at TR2 collector is pushed up in frequency as P1 is moved down most desirable for stability. Simultaneously the local NFB through Cdom linearises the VAS.

Figure 7.1: (a) The traditional Miller method of making a dominant pole. (b) Shunt compensation shows a much less satisfactory method the addition of capacitance to ground from the VAS collector. (c) Inclusive Miller compensation. (d) Two-pole compensation

Assuming that input-stage transconductance is set to a plausible 5 mA/V, and stability considerations set the maximal 20kHz open-loop gain to 50 dB, then from Equations 3.1 3.3 on pages 63 and 64, Cdom must be 125 pF. This...