11.1 INTRODUCTION

A phase locked loop (PLL) is a device capable of generating an output signal having a frequency that is synchronized to that of an input reference signal. The generated frequency has good noise performance and is of high accuracy. A PLL is used for locking a noisy and imprecise signal to a more precise and less noisy signal, which usually has a lower frequency. Furthermore, a PLL can be implemented on a monolithic chip making it suitable for wireless systems, where size and power dissipation are of high importance. PLLs are extensively used in frequency synthesizers. About 98% of the frequency synthesizer market is based on PLL technology.

The PLL suppress the voltage controlled oscillator (VCO) noise within the bandwidth of its loop, any VCO noise outside the bandwidth of the loop passes virtually unattenuated.

The focus of this chapter is to present different PLL architectures, we also discuss the important PLL parameters. In section 11.2, we present the basic structure of the PLL, and its theory of operation. In section 11.3, we consider different types of phase detectors and their impact on the performance of the phase locked loop. In section 11.4, we present different types of frequency dividers. Section 11.5 discusses the theory of operation of oscillators along with some examples of oscillator circuits.

11.2 OPERATION OF THE PHASE LOCKED LOOP

A phase locked loop, as shown in Figure 11.1, typically consists of a phase detector (PD), a loop filter, a voltage controlled oscillator (VCO), and...