Overview

The performance of data links is largely dominated by the characteristics of wire channels over which information is transmitted, especially when data rate reaches multiple Gb/s. Typical wire channels encountered in VLSI systems include printed-circuit-board traces, package lead frames, bonding wires, bonding pads, on-chip metal layers, silicided poly layers, silicided n+ and p+ diffusion layers, vias connecting different metal layers, and contacts connecting the lowest metal layer and diffusion regions or poly layers. Although the rapid reduction of device feature size has resulted in a significant improvement in the intrinsic cutoff frequency of MOS transistors, the resistance of on-chip wire channels has also increased significantly arising from the reduced wire width and height, and frequency-dependent skin effect [86]. The increased frequency of signals further demands that the inductive effect of wire channels be considered fully as the performance of wire channels at high frequencies is largely dominated by the inductive effect [87].

This chapter is concerned with the modeling and design considerations of wire channels. Sections 3.1 examines the resistance of wire channels. An emphasis is given to the skin effect of conductors. Section 3.2 is concerned with the capacitance of wire channels. We are particularly interested in the area and fringe capacitances of microstrip lines as they are the most widely encountered wire channels both on a chip and on a board. In Section 3.3, the inductance of wire channels is investigated in detail. Inductive effect has long been one of most critical design concerns of printed circuit...