CMOS Current-Mode Circuits for Data Communications

Unlike phase-picking approaches where the data and clock information is recovered from multiple samples per data eye blindly, in phase-tracking approaches, the phase difference between either the edge or the center of the received data eye and the edge of the sampling clock generated by either a delay locked loop or a phase-locked loop at the receiver is measured by a phase-frequency detector. Two samplers, namely the data sampler that samples the center of the data eye and the timing sampler that samples the edge of the data eye, are employed to sample the incoming data eye. The output of the phase-frequency detector drives a downstream charge pump whose output adjusts the delay of a downstream delay line or a voltage-controlled oscillator such that the clock edge of the sampling clock is placed at the data transition or the center of the data eye. Once the phase difference is zero, the data sample at the center of the data eye provides the recovered data whereas that at the edge of the data eye provides the timing information of the received data. Note that because at least two samples are required per data eye, phase-tracking clock and data recovery is also known as tracked oversampling clock and data recovery[156, 157].
Fig. 6.20 shows a typical configuration of a 2x-oversampling phasetracking clock and data recovery using phase-locked loops. The basic configuration of 2x-oversampling phase-tracking clock and data recovery using delay-locked loops is shown in Fig.