TABLE OF CONTENTS In a practical logic circuit the inputs, and consequently the outputs of the gates comprising the logic circuit change state with time and it is convenient to represent the changing inputs and outputs by waveforms referred to as timing diagrams such as that shown in Figure 7.22. [*]
In the timing diagrams of Figure 7.22 it is assumed that the first two represent the inputs are A and B and those below represent their complements, ANDing, ORing, NANDing, NORing, XORing, and XNORing.
For the logic diagram of Figure 7.23(a), the inputs A and B vary with time as shown in Figure 7.23(b). Sketch the timing diagram for the output C in the time interval T 1 ?T ?T 2.
Solution:
From the logic diagram of Figure 7.23(a), 
, that is, the logic diagram represents an XOR gate implemented with NAND gates. The timing diagram for the output C is shown in Figure 7.24.
We can also use a Simulink model to display the timing diagrams of the inputs and the output. Figure 7.24A is an example using a Signal Builder block. whose the waveforms of Figure 7.24B serve as inputs to an XOR gate, and these inputs and the output waveform are displayed on the Scope block of...
