Digital Circuit Analysis and Design with Simulink Modeling and Introduction to CPLDs and FPGAs, Second Edition

7.5: Design of Common Logic Circuits

7.5 Design of Common Logic Circuits

The following procedures are essential in designing logic circuits from the specifications or problem statements.

  1. The problem must be clearly stated.

  2. A truth table must be prepared from the problem description.

  3. A K-map can be used to simplify the logic expression.

  4. A logic diagram can be drawn from the simplest logic expression.

    The examples that follow will illustrate these procedures.

7.5.1 Parity Generators/Checkers

The following example illustrates the design steps for parity generators.

Example 7.18

Design a combinational logic circuit to generate odd parity for the BCD code, i.e., a logic circuit that will generate the odd parity bit for any 4-bit combination of the BCD code.

Solution:

From the problem statement we conclude that the logic circuit we are asked to design will have 4 inputs, say A, B C, and D, where these inputs represent the weights of the BCD code (A=msb and D=lsd), and one output P representing the parity bit. This can be represented by the block diagram of Figure 7.40.


Figure 7.40: 4-bit odd parity generator for Example 7.18

Next, we construct the truth table shown as Table 7.1, and since the problem statement made no mention of the illegal BCD (1010, 1011, 1100, 1101, 1110, and 1111) combinations we treat these as don t cares.

Table 7.1: 4-bit odd parity generator

Inputs

Output

A

B

C

D

P

0

0

0

0

1

0

0

0

1

0

0

0

1

0

0

0

0

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