TABLE OF CONTENTS The solder joint reliability of various wafer-level chip-scale packages (WLCSPs) on organic printed circuit board (PCB)/substrate is the focus of discussion in this chapter,1 117 since the compliance of lead-free solder joints is so small and the thermal expansion mismatch between the silicon chip and epoxy PCB/substrate is so large. Specifically, the useful thermal cycling test and modeling results provided by Hitachi, Motorola, and Flip Chip Technology are presented in this chapter. It should be noted that the surface-mount technology (SMT) assembly of lead-free solder-bumped WLCSPs on PCB/substrate will be discussed in Chaps. 11 through 16. In this chapter, the solders on the chip before it is joined to the substrate are called solder bumps. After the solder bumps have been reflowed on the PCB/substrate, they are called solder joints.
The effects of WLCSP stress-relaxation layer on the SnAgCu solder joint reliability and high-frequency applications have been determined by Hitachi,114 whose useful results are presented in this section.
The finite element analysis model of Hitachi s SnAgCu WLCSP with a stress-relaxation layer on a PCB (Fig. 2.20) is shown in Fig. 3.1. Due to double symmetries, only one-fourth of the structure is modeled. The distance from the neutral point (DNP) to a corner solder joint is 4.7 mm, as shown in Table 3.1, where information on chip size, pin layout, and the PCB are also given. The thermal cycling is between ?
