TABLE OF CONTENTS The lead-free solder bumps discussed in Chaps. 2 and 3 are just one of many different kinds of chip (wafer)-level interconnects.1 19 In this chapter, solderless chip (wafer)-level interconnects such as electroless Ni-P-immersion Au bumps, electroplated gold bumps, electroplated copper bumps, electroplated copper wires, wire-bonding gold wires (microsprings), wire-bonding gold stud bumps, and wire-bonding copper stud bumps will be discussed.
In this section the wafer size for Ni-Au bumps, electroplated Au bumps, and electroplated Cu bumps is 6 in. The chip is 0.5 in (12.7 mm) square and 25 mil (0.64 mm) thick. The street width between all the chips is 6 mil (0.15 mm). The chip has 8-mil (0.2-mm) square pads and 14-mil (0.36-mm) pitch. All of the pads are arranged symmetrically around the perimeter of the chip and are interconnected via traces on the chip in an alternating pattern so as to provide daisy-chained connections when the chip is attached to the FR-4 printed circuit board (PCB).
The silicon wafer consists of a patterned aluminum layer on a layer of silicon dioxide that is covered with a patterned silicon nitride passivation layer. The wafer fabrication process flow starts with a 0.25- ?m layer of silicon dioxide deposited by plasma enhanced chemical vapor deposition on a <111> silicon substrate. For the metal layer, a 0.85- ?m layer of Al-1%Si-0.1%Ti alloy is sputtered over the silicon dioxide. The metal pattern is then defined by coating...
