This chapter will deal with frequency synthesizers appropriate for medium-and high-performance HF SSB radios. Space limitations preclude a thorough treatise on synthesizer design, many aspects of which are covered in the literature (see reference ^{[1] [5]}, for example). We will concentrate on tuning speed, phase noise, spurious output signals, and the generation of small frequency steps needed in the HF band. The most important phase-lock loop (PLL) configurations will be discussed; newer, all-digital techniques for producing small steps will be introduced, and the methods of combining these with traditional loops will be shown.

The method of analysis is, we believe, unique. Most of the literature on synthesizers presents either a detailed mathematical analysis of single loops or a discussion of multiloop synthesizers that have already been designed. Here, we will concentrate on the important middle ground, where it is assumed that the individual building blocks exist to build a loop and the designer must understand in detail the overall loop properties and the way loops relate to each other. Block diagrams will be used extensively; the blocks that make up a loop will be assigned terminal characteristics and analyzed. Computer analysis will be extensively used. Graphic results will be shown for each configuration, and it will become clear why certain arrangements are preferred and what level of complexity is required to produce the desired output.