The basic steps any microprocessor instruction goes through have changed little since the first pipelined processors. An instruction must be fetched. It must be decoded to determine what type of instruction it is. The instruction is executed and the results stored. What has changed is that steps have been added to try and improve performance, such as register renaming and out-of-order scheduling. The total number of cycles in the pipeline has increased to allow higher clock frequency. As an example of how a processor microarchitecture works, this section describes in detail what actions occur during each step of the original Pentium 4 pipeline.

The Pentium 4 actually has two separate pipelines, the front-end pipeline, which translates macroinstructions into uops, and the execution pipeline, which executes uops.

The front-end pipeline has the responsibility for fetching macroinstructions from memory and decoding them to keep a trace cache filled with uops. The execution pipeline works only with uops and is responsible for scheduling, executing, and retiring these instructions. Table 5-1 shows the number of clock cycles allocated for each step in the execution pipeline for a total of 20 cycles. This is the best case pipeline length with many instructions taking much longer. Most importantly 20 cycles is the branch mispredict penalty. It is the minimum number of cycles required to fetch and execute a branch, to determine if the branch prediction was correct, and then to start fetching from the correct address if the prediction was wrong. Intel...