TABLE OF CONTENTS This chapter discusses the process of converting a microarchitectural design into a hardware description language (HDL) model. Validation of the logic design model is described as well as design automation flows, which allow HDL to be converted into layout. By hand logic minimization is demonstrated for combinational and sequential circuits.
Upon completion of this chapter the reader will be able to:
Be familiar with the different levels of HDL abstraction.
Describe the trade-offs of different design automation flows.
Describe the goals and difficulties of pre-silicon validation.
Be familiar with the symbols and behavior of common logic gates.
Perform logic minimization of combinational or sequential circuits using Karnaugh maps (K-maps).
Microarchitectural choices will have the greatest impact on the processor's performance and die area, but these choices are almost never black and white. Microarchitecture must trade off performance with die area and complexity. The result of the microarchitecture design is typically block diagrams showing the interactions of the processor's different components and a written specification describing their algorithms. Some simple simulations or hand calculations may be performed to estimate performance, but from this set of documents there is no easy way to determine whether the processor will actually produce the correct result for different programs. The task of logic design is to turn a microarchitectural specification into a logical model that can be tested for correctness.
Very early computer designs used few enough transistors in their components that circuit design could be performed directly from the design...
