What are the causes of pipeline breaks?

What effect will increasing the pipeline length likely have on frequency, IPC, and performance?

How does HyperThreading improve performance?

Explain Amdahl's law in words.

What are some commonly used measures of processor performance? What are their drawbacks?

What are the three causes of cache misses? How can each be reduced?

Why is cache coherency necessary? What are the four states of MESI cache coherency protocols?

How can processors avoid control dependencies?

How can processors avoid data dependencies?

What are the trade-offs in choosing an instruction cache or a trace cache?

[Discussion] How will data dependencies, control dependencies, and resource conflicts affect processors trying to achieve high frequency through deep pipelines? How will wide issue superscalar processors be affected?

[Discussion] Assuming the gap between processing speed and main memory latency continues to grow, computer performance may become dominated by memory access time. Which microarchitectural features would improve performance in this case? Which would not? How might a computer with a processor 100 times faster than today, but memory only twice as fast be designed differently than current computers?