TABLE OF CONTENTS The inductive characteristics of electric circuits are described in Chapter 2. Both accurate and efficient characterization of on-chip interconnect inductance is difficult, as discussed in the previous chapter. The objective of this chapter is to demonstrate that the task of inductance characterization, however, is considerably facilitated in certain interconnect structures. These results will be used in Chapter 9 to provide insight into the inductive properties of power distribution grids.
The chapter is organized as follows. A brief overview of the problem is presented in Section 3.1. The dependence of inductance on line length is discussed in Section 3.2. The inductive coupling of parallel conductors is described in Section 3.3. Application of these results to the circuit analysis process is discussed in Section 3.4. The conclusions are summarized in Section 3.5.
IC performance has become increasingly constrained by on-chip interconnect impedances. Determining the electrical characteristics of the interconnect at early stages of the design process has therefore become necessary. The layout process is driven now by interconnect performance where the electrical characteristics of the interconnect are initially estimated and later refined. Impedance estimation is repeated throughout the circuit design and layout process and should, therefore, be computationally efficient.
The inductance of on-chip interconnect has become an important issue due to the increasing switching speeds of digital integrated circuits [61]. The inductive properties must, therefore, be effectively incorporated at all levels of the design, extraction, and simulation phases in the development of high speed ICs.
Operating an inductance extractor within...
