Power Distribution Networks with On-Chip Decoupling Capacitors
By Eby G. Friedman

List of Tables

Chapter 5: High Performance Power Distribution Systems

Table 5.1: Parameters of a case study power distribution system

Chapter 6: Decoupling Capacitan

Table 6.1: Four common types of on-chip decoupling capacitors in a 90nm CMOS technology

Chapter 9: Inductive Properties of On-Chip Power Distribution Grids

Table 9.1: Inductive characteristics of power/ground grids with a 1000 ?m length and a 40 ?m line pair pitch operating at 1 GHz and 100 GHz

Chapter 12: Scaling Trends of On-Chip Power Distribution Noise

Table 12.1: Ideal scaling of CMOS circuits [280]
Table 12.2: Scaling analyses of power distribution noise

Chapter 15: On Chip Power Distribution Grids with Multiple Supply Voltages

Table 15.1: Impedance characteristics of power distribution grids with SSSG
Table 15.2: Impedance characteristics of interdigitated power distribution grids with DSSG
Table 15.3: Impedance characteristics of interdigitated power distribution grids with DSDG
Table 15.4: Impedance characteristics of Type I paired power distribution grids with DSDG
Table 15.5: Impedance characteristics of Type II paired power distribution grids with DSDG

Chapter 16: Decoupling Capacitors for Multi-Voltage Power Distribution Systems

Table 16.1: Case study of the impedance of a power distribution system
Table 16.2: Tradeoff between the magnitude and frequency range of the voltage response

Chapter 17: On-chip Power Noise Reduction Techniques in High Performance ICs

Table 17.1: Ground bounce reduction as a function of the separation between the noisy and noise sensitive circuits
Table 17.2: Ground bounce reduction for different values of parasitic resistance of the on-chip low noise ground

Chapter 18: Effective Radii...

Copyright Springer Science+Business Media, LLC 2008 under license agreement with Books24x7
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