In Chapter 5, we discussed various combinational circuits that are commercially available in IC packages. We also saw how other combinational circuits and Boolean functions are realized with the help of these commercially available IC packages. With the advent of large-scale integration technology, it has become feasible to fabricate large circuits within a single chip. One such consequence of this technology is the Programmable Logic Devices or PLDs.

The advantages of using programmable logic devices are:

1. Reduced space requirements.
2. Reduced power requirements.
3. Design security.
4. Compact circuitary.
5. Short design cycle.
6. Low development cost.
7. Higher switching speed.
8. Low production cost for large-quantity production.

In earlier chapters, we have seen that any Boolean function or combinational circuit can be represented by sum of the products form or sum of the required minterms. It was also shown that a decoder generates 2ⁿ minterms for n number of input variables and required minterm outputs of a decoder are fed to an OR gate to obtain a desired function. This fact leads to the development of IC packages with larger integration that contain decoders with a number of OR gates or one single chip containing a large number of basic gates AND, OR, and NOT. These ICs are programmed according to desired functions by the manufacturers or the designers. Another advantage of employing these ICs is that one single IC can generate multiple outputs, thus reducing the board space, interconnections, and power consumption.

Figure 6.1

The general structure of programmable logic devices is illustrated in Figure 6.1. The inputs to the PLD are applied to a set of buffers/inverters. Buffers/inverters provide the true values of the inputs as well as the complemented values of the inputs. In addition, they also provide the necessary drive for the AND array, which consists of a large number of AND gates that follow next to buffers/inverters. The AND array produces p numbers of product terms from n numbers of input variables and their complements. These product terms are fed to the OR array, which follows next. The OR array also consists of several numbers of OR gates and realizes a set of m numbers of outputs at sum of the products form.

Programmable logic devices are broadly classified as three types of devices Read Only Memory or ROM, Programmable Logic Array or PLA, and Programmable Array Logic or PAL. PLDs serve as the general circuits for realization of a set of Boolean functions. One or both of the arrays of PLDs are programmable in the sense that the logic designer can select the connections within the array. In ROM and PAL, one of the arrays are programmable whereas both the arrays are programmable for PLA. The following table summarizes which arrays are programmable for the various PLDs.

In a programmable array, the connections of gates can be selected. The simple approach for fabricating the programmable gate is to employ fuse links at each of the inputs of the gate as demonstrated in Figure 6.2(a). Some of the fuses are programmed to blow out to achieve the desired output from the gate. As an example, if the desired output of the gate is BC, then fuses at A and D are to be blown out as shown in Figure 6.2(b). Similarly, the same gate may be programmed for the function ACD, if only the fuse at input B is blown out. Therefore, with the blowing of fuses with proper programming, the same gate can generate several Boolean functions.

Figure 6.2(a) Figure 6.2(b)

Although various schemes are used at fabrication of these types of gate arrays, this simple approach is assumed here to understand the function of PLDs. It should also be assumed that the open inputs of an AND gate array are connected to logic 1 and open inputs of an OR gate are connected to logic 0.