The basic concepts of programmable logic devices and programmable gate arrays have been discussed. With the development of these devices, complex digital systems have become possible to be designed. However, high-level design techniques and computer-aided tools are required to realize efficient PLD and FPGA implementations. The emergence of these devices has revolutionized the design of digital systems similar to the emergence of microprocessor or microcontrollers. The programmable logic concept has provided the power to design one's custom ICs which cannot be copied by others.

6.1 Define PLD. What are the advantages PLD?

6.2 What are the types of PLD?

6.3 List the applications of PLD.

6.4 What is PLA? How does it differ from ROM? Draw the block diagram of PLA.

6.5 What is PAL? How does it differ from ROM? Draw the block diagram of PAL.

6.6 What are the advantages of FPGA over other types of PLD?

6.7 Draw the internal logic construction of 32 × 4 ROM.

6.8 Give the comparison among PROM, PLA, and PAL.

6.9 How many words can be stored in a ROM of capacity 16K × 32?

6.10 What is the bit storage capacity of a 512 × 4 ROM?

6.11 State the differences among ROM, PROM, EPROM, and EEPROM.

6.12 Explain the difference between ROM and RAM.

6.13 What do a dot and an × represent in a PLD diagram?

6.14 How many memory locations are there for address values?

(a) 0000 to 7FFF, (b) C000 to C3FF, or (c) A000 to BFFF.

6.15 Specify the size of a ROM for implementation of the following combinational circuit.

(a) a binary multiplier for multiplication of two 4-bit numbers, or (b) a 4-bit
adder/subtractor.

6.16 Implement the following Boolean expressions using ROM.

F₁ (A, B, C) = ∑ (0, 2, 4, 7), F₂ (A, B, C) = ∑ (1, 3, 5, 7)

6.17 Implement the following Boolean expressions using PLA.

F₁ (A, B, C) = ∑ (0, 1, 3, 5), F₂ (A, B, C) = ∑ (0, 3, 5, 7)

6.18 Implement the following Boolean expressions using PAL.

F₁ (A, B, C, D) = ∑ (1, 2, 5, 7, 8, 10, 12, 13)

F₂ (A, B, C, D) = ∑ (0, 2, 6, 8, 9, 14)

F₃ (A, B, C, D) = ∑ (0, 3, 7, 9, 11, 12, 14)

F₄ (A, B, C, D) = ∑ (1, 2, 4, 5, 9, 10, 14)

6.19 Tabulate the PLA programmable table for the four Boolean functions listed below.

A (X, Y, Z) = ∑ (0, 1, 2, 4, 6)

B (X, Y, Z) = ∑ (0, 2, 6, 7)

C (X, Y, Z) = ∑ (3, 6)

D (X, Y, Z) = ∑ (1, 3, 5, 7)

6.20 Design a BCD-to-Excess-3 code converter using (a) PROM, (b) PLA, and (c) PAL.

6.21 Design an Excess-3-to-BCD code converter using (a) PROM, (b) PLA, and (c) PAL.

6.22 Design a BCD-to-seven segment display decoder using (a) PROM, (b) PLA, and (c) PAL.

6.23 Tabulate the PLA programmable table for the four Boolean functions listed below.

A (X, Y, Z) = ∑ (1, 2, 4, 6)

B (X, Y, Z) = ∑ (0, 1, 6, 7)

C (X, Y, Z) = ∑ (2, 6)

D (X, Y, Z) = ∑ (1, 2, 3, 5, 7)

6.24 Following is a truth table of a three-input, four-output, combinational circuit. Tabulate the PAL programming table for the circuit and mark the fuse map in the diagram.

6.25 Design a code converter that converts 2421 code to BCD as well as to Excess-3 code using
(a) PROM, (b) PLA, and (c) PAL.