Digital Principles & Logic Design

Section 6.2 - PLD Notation

To indicate the connections to an AND array and an OR array of a PLD, a simplified notation is frequently used. The notation is illustrated in Figures 6.3(a) and 6.3(b). Rather than drawing all the inputs to the AND gate or OR gate, a single line is drawn to the input to the gate. The inputs are indicated by the right-angled lines. The connected input variables are indicated by cross (×) at junctions and unconnected inputs are left blank. The cross-marked junctions represent the fusible joints while junctions with dots indicate permanent junctions that are not fusible.


Figure 6.3(a)
All fuses are intact.



Figure 6.3(b)
Fuses A and D are blown to obtain function F=BC.

UNLIMITED FREE
ACCESS
TO THE WORLD'S BEST IDEAS

SUBMIT
Already a GlobalSpec user? Log in.

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

Customize Your GlobalSpec Experience

Category: Digital Multimeters
Finish!
Privacy Policy

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.