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Section 6.2 - PLD Notation
By A. Saha
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From Digital Principles & Logic Design
To indicate the connections to an AND array and an OR array of a PLD, a simplified notation is frequently used. The notation is illustrated in Figures 6.3(a) and 6.3(b). Rather than drawing all the inputs to the AND gate or OR gate, a single line is drawn to the input to the gate. The inputs are indicated by the right-angled lines. The connected input variables are indicated by cross (×) at junctions and unconnected inputs are left blank. The cross-marked junctions represent the fusible joints while junctions with dots indicate permanent junctions that are not fusible.  Figure 6.3(a) All fuses are intact.
© 2006-2009 Infinity Science Press. All rights reserved.
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