![]() | This text/reference provides students and practicing engineers with an introduction to the classical methods of designing electrical circuits, but incorporates modern logic design techniques used in the latest microprocessors, microcontrollers, microcomputers, and various LSI components. The book provides a review of the classical methods e.g., the basic concepts of Boolean algebra, combinational logic and sequential logic procedures, before engaging in the practical design approach and the use of computer-aided tools. The book is enriched with numerous examples (and their solutions), over 500 illustrations, and includes a CD-ROM with simulations, additional figures, and third party software to illustrate the concepts discussed in the book. |
Section 6.2 - PLD Notation
To indicate the connections to an AND array and an OR array of a PLD, a simplified notation is frequently used. The notation is illustrated in Figures 6.3(a) and 6.3(b). Rather than drawing all the inputs to the AND gate or OR gate, a single line is drawn to the input to the gate. The inputs are indicated by the right-angled lines. The connected input variables are indicated by cross (×) at junctions and unconnected inputs are left blank. The cross-marked junctions represent the fusible joints while junctions with dots indicate permanent junctions that are not fusible.

Figure 6.3(a) All fuses are intact.

Figure 6.3(b) Fuses A and D are blown to obtain function F=BC.

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