The final programmable logic device to be discussed is the Programmable Array Logic or PAL device. The general structure of this device is similar to PLA, but in a PAL device only AND gates are programmable. The OR array in this device is fixed by the manufacturer. This makes PAL devices easier to program and less expensive than PLA. On the other hand, since the OR array is fixed, it is less flexible than a PLA device.

Figure 6.22

Figure 6.23

Figure 6.22 represents the general structure of a PAL device. It has n input lines which are fed to buffers/inverters. Buffers/inverters are connected to inputs of AND gates through programmable links. Outputs of AND gates are then fed to the OR array with fixed connections. It should be noted that, all the outputs of an AND array are not connected to an OR array. In contrast to that, only some of the AND outputs are connected to an OR array which is at the manufacturer's discretion. This can be clarified by Figure 6.23, which illustrates the internal connection of a four-input, eight AND-gates and three-output PAL device before programming. Note that while every buffer/inverter is connected to AND gates through links, F₁-related OR gates are connected to only three AND outputs, F₂ with three AND gates, and F₃ with two AND gates. So this particular device can generate only eight product terms, out of which two of the three OR gates may have three product terms each and the rest of the OR gates will have only two product terms. Therefore, while designing with PAL, particular attention is to be given to the fixed OR array.