 | This text/reference provides students and practicing engineers with an introduction to the classical methods of designing electrical circuits, but incorporates modern logic design techniques used in the latest microprocessors, microcontrollers, microcomputers, and various LSI components. The book provides a review of the classical methods e.g., the basic concepts of Boolean algebra, combinational logic and sequential logic procedures, before engaging in the practical design approach and the use of computer-aided tools. The book is enriched with numerous examples (and their solutions), over 500 illustrations, and includes a CD-ROM with simulations, additional figures, and third party software to illustrate the concepts discussed in the book. |
TABLE OF CONTENTS Digital Principles & Logic Design
Section 6.8 - Generic Array Logic Devices
The Generic Array Logic or GAL device is another type of configurable PAL device. GAL devices are intended as pin-to-pin replacements for a wide variety of PAL devices. It is designed to be compatible, all the way to the fuse level, for any simpler PAL which can be directly implemented in the GAL device. In this device, the OR gate is considered to be a part of a macrocell to obtain various types of I/O configurations found in the PAL devices that it is designed to replace.
Another family of devices that are intended for PAL replacements are programmable electrically erasable logic or PEEL devices. Its output macrocell can be programmed for numerous types of I/O configurations.
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