TABLE OF CONTENTS In this chapter we address the test scheduling problem for system-on-chip designs. Different from previous approaches where it is assumed that all tests will be performed until completion, we consider the cases where the test process will be terminated as soon as a defect is detected. This is common practice in production test of chips. The proposed technique takes into account the probability of defect-detection by a test in order to schedule the tests so that the expected total test time will be minimized. It supports different test bus structures, test scheduling strategies (sequential scheduling vs. concurrent scheduling), and test set assumptions (fixed test time vs. flexible test time). Several heuristic algorithms have been developed and experiments performed to demonstrate their efficiency.
The cost of developing electronic systems is increasing and a significant part of the cost is related to the testing of the systems. One efficient way to reduce this cost is therefore to reduce the testing cost. Test cost reduction can be achieved by minimizing the testing time of the system. An efficient ordering, test scheduling, of the execution of the test sets will minimize the total testing time.
The core-based design technique is another approach to reduce the increasing development costs. With such a technique, pre-designed and preverified blocks of logic, so called cores, are integrated to a complete system, which can be placed on a single die to form a system-on-chip (SOC). To test a SOC, a test bus is used for the...
