TABLE OF CONTENTS We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.
The testing of System-on-Chip (SOC) is a crucial and time consuming problem due to the increasing design complexity. Therefore it is important to provide the test designer with support to develop an efficient test solution.
The work-flow for a test designer developing a test solution consists typically of two consecutive parts: an early design space exploration and an extensive optimization for the final solution. During the process, conflicts and limitations must be carefully considered. For instance, tests may be in conflict with each other due to the sharing of test resources; and power consumption must be controlled, otherwise the system may be...
