List of Figures

Chapter 1: Introduction

Figure 1: The number of transistors for some Intel processors (points) and the Moore s law prediction (straight line) [107, 198].
Figure 2: The system-on-chip design flow, the involved persons in (a) a sequential design flow and (b) in an integrated design flow.
Figure 3: The predicted cost per transistor versus the predicted test cost per transistor [106].

Figure 4: Design flow.
Figure 5: Design flow in a core-based design environment (a) traditional and (b) proposed.
Figure 6: System design.
Figure 7: Clocked systems. (a) a finite state machine (FSM); (b) a pipelined system.
Figure 8: Single phase clocking and its parameters.
Figure 9: Example illustrating high current and power [277].
Figure 10: Distributed clock-tree where the logic is omitted.
Figure 11: Gantt chart.
Figure 12: Simulated Annealing algorithm.
Figure 13: Genetic algorithm.

Figure 14: An AND gate with a SA1 at input A.
Figure 15: An example circuit.
Figure 16: (a) Truth table; (b) singular cover.
Figure 17: The singular covers for a circuit.
Figure 18: (a) Singular cover and (b) D-cubes for an AND-gate.
Figure 19: An example circuit.
Figure 20: A circuit with both blocks of combinational logic and sequential elements.
Figure 21: Test point insertion, (a) original circuit, (b) observation point, (c) 1-control point, and (d) 0-control point.
Figure 22: A circuit with both blocks of combinational logic and sequential elements.
Figure 23: A scan path.
Figure 24: Scan chain testing (a) without test vector...

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